The present invention relates to a semiconductor memory device, and more particularly, to a combined memory system formed by a DRAM and a nonvolatile memory that is mainly installed in mobile devices.
Portable devices, such as a cellular phone, a personal handyphone system (PHS), or a personal digital assistant (PDA), which is provided with communication functions, have become compact. Further, the amount of communication data handled by portable terminals has been increasing. For example, in addition to conversation functions, a cellular phone functions to transmit text data and image data. Further, it is predicted that a cellular phone will be employed as an information terminal that uses the Internet (portable personal computer).
Additionally, the communication speed of a portable device has increased, and the miniaturization of the portable devices has resulted in the incorporation of smaller batteries. Accordingly, a memory installed in a portable device is required to have high operating speed, large capacity, and low power consumption. It is further required that the cost of cellular phone components be reduced to make the cellular phone more price competitive. Thus, it is required that a working memory be inexpensive and have a large capacity.
An SRAM having a predetermined memory capacity (e.g., about four megabits) has been installed in a portable terminal such as cellular phone to function as a working memory that stores necessary data during operation. However, the employment of a flash memory and a DRAM in lieu of the SRAM has been proposed to increase the amount of communication data and to increase communication speed. A DRAM is compatible with an SRAM of an asynchronous memory system.
The DRAM is advantageous in that its cost per bit is low and in that it performs read/write operations at high speeds. However, the DRAM consumes power to maintain data when in a standby state. The power consumption in the standby state is several hundreds of microamperes when the DRAM is in a cell refresh mode in which the DRAM automatically and continuously maintains the data of the entire memory. When the DRAM is in a standby mode in which written data need not be held, the power consumption is several tens of microamperes.
A flash memory is advantageous in that it does not require refreshing and in that its power consumption in a standby mode is several microamperes. However, the flash memory requires several microseconds to several tens of microseconds for data to be written. Thus, it takes time to write data.
Accordingly, the DRAM is used as a large capacity, high speed working memory during communication. The data that is to be held in a standby state is transferred from the DRAM to the flash memory before deactivating the DRAM. By operating in such manner, the power consumption of a cellular phone decreases.
When the cellular phone shifts from a standby state to a conversation state, the data in the flash memory must be rewritten to the DRAM after reactivating the DRAM. Such operation produces a wait (system busy) time, which in turn, decreases the performance of the entire system (cellular phone).
To solve such shortcoming, a DRAM provided with a partial refresh function may be employed. The partial refresh function refreshes data of only predetermined memory sections. In a cellular phone, when the power is on, as long as some pieces of data are held, the remaining data need not be held. Therefore, the memory area to which data is to be held may be designated. Alternatively, the data that is to be held may be written to a memory section that is refreshed. The power consumption of such DRAM is lower than that of a DRAM that refreshes the entire memory cells. Further, the wait time required for the data in the flash memory to be rewritten to the DRAM decreases. Accordingly, the performance of the cellular phone does not decrease.
However, when low power consumption is an important factor in a portable device, it is preferred that that the DRAM be completely deactivated during the standby mode. Further, a system that selectively performs partial refreshing or complete deactivation of the DRAM in accordance with the state of the portable device may be designed to decrease the wait time and power consumption. In such manner, a semiconductor memory device that enables a user to set different low power consumption modes is desired.
It is an object of the present invention to provide a semiconductor memory device that decreases power consumption and increases performance.
To achieve the above object, the present invention provides a semiconductor memory device including a plurality of memory cells that undergo refreshing to maintain data. The semiconductor memory device includes a normal operation mode for performing normal operation with the memory cells and a plurality of low power consumption modes for decreasing power consumption when the semiconductor memory device is in a standby state. The semiconductor memory device includes a mode setting circuit for setting one of the low power consumption modes.
In a further perspective, the present invention is a semiconductor memory device. The semiconductor memory device includes a memory core including a plurality of memory cells that undergo refreshing to maintain data. The semiconductor memory device includes a normal operation mode for performing normal operation with the memory cells and a plurality of low power consumption modes for decreasing power consumption when the semiconductor memory device is in a standby state. An internal power supply circuit is connected to the memory core for supplying the memory core with an operational voltage. The plurality of low power consumption modes includes one of a first low power consumption mode and a second low power consumption mode and a third low power consumption mode. The first low power consumption mode stops the refreshing of all of the memory cells and stops the operation of the internal power supply circuit. The second low power consumption mode stops the refreshing of all of the memory cells and continues the operation of the internal power supply circuit. The third low power consumption mode refreshes some of the memory cells and continues the operation of the internal power supply circuit. The semiconductor memory device includes a mode setting circuit for setting one of the low power consumption modes.
In a further perspective, the present invention is a semiconductor memory device. The semiconductor memory device includes a plurality of memory cells arranged in a plurality of memory sections. The memory cells undergo refreshing to maintain data. The semiconductor memory device includes a refresh mode for refreshing the memory cells in at least one of the memory sections. Each of the memory sections have an inherent refreshing characteristic. A selection circuit selects at least one of the memory sections that has the best refreshing characteristic.
In another perspective, the present invention is a semiconductor device. The semiconductor device includes a first semiconductor memory device that does not require data maintaining and a second semiconductor device connected to the first semiconductor memory device. The second semiconductor memory device includes a plurality of memory cells that undergo refreshing to maintain data. The semiconductor memory device includes a normal operation mode for performing normal operation with the memory cells and a plurality of low power consumption modes for decreasing power consumption when the semiconductor memory device is in a standby state. The second semiconductor memory device includes a mode setting circuit that sets one of the low power consumption modes.
In a further perspective, the present invention is a semiconductor memory device. The semiconductor memory device includes a plurality of memory cells that are refreshed to maintain data. The semiconductor memory device includes a normal operation mode for performing normal operation with the memory cells and a plurality of low power consumption modes for decreasing power consumption when the semiconductor memory device is in a standby state. A command decoder receives a command and generates a first program mode signal and a normal operation mode signal based on the command. An entry control circuit is connected to the command decoder for receiving the first program mode signal from the command decoder and generating a program mode entry signal based on the first program mode signal. A mode setting circuit is connected to the entry control circuit to set one of the low power consumption modes in response to the program mode entry signal.
In a further perspective, the present invention is a semiconductor memory device. A plurality of memory cells are refreshed to maintain data. The semiconductor memory device includes a normal operation mode for performing normal operation with the memory cells and a plurality of low power consumption modes for decreasing power consumption when the semiconductor memory device is in a standby state. A mode setting circuit generates a refresh operation mode signal corresponding to one of the low power consumption modes. A refresh control circuit is connected to the mode setting circuit to compare a setting address of the memory cells that are to be refreshed with the refresh counter address in response to the refresh operation mode signal and to generate the refresh signal when the setting address and the refresh counter address match.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.